An ISA (Industrial Standard Architecture) bus is a bus standard formulated by the IBM Corporation for PCs. An ISA bus has a clock frequency of 8 MHz and a maximum data transmission rate of 16 M/S. The ISA bus is low in the transmission rate and takes up a large share of CPU resources. With development of bus technologies, the ISA bus is gradually replaced with the high-speed CPCI bus.
A CPCI (Compact Peripheral Component Interconnect) bus is a high-speed bus interface specification standard proposed by the International Industrial Computer Manufacturer's Group in the last century. Based on electrical interface specification of the standard PCI bus, the CPCI bus is a bus with high compatibility and high reliability; and the bus clock frequency thereof can reach 66 MHz.
The ISA buses are highly compatible. With years of technology accumulation, there is a large quantity of mature products of the ISA bus. Due to the hot-pluggable property, high compatibility, high reliability and high transmission rate, the CPCI buses have been widely applied in traction controllers of railway vehicles. However, ISA bus interfaces are still extensively applied in MVB communication devices of railway vehicles. To realize stable and reliable communication between a high-speed CPCI bus and a low-speed ISA bus, providing a bus converter between a CPCI bus and an ISA bus is a challenge which all railway vehicle development professionals face.
The key technology for designing a stable and reliable communication between a high-speed CPCI bus and a low-speed ISA bus is to design a local interface of the CPCI bus to match the ISA bus interface. At present, the most widespread implementation solution is to use dedicated bridge chips manufactured by PLX and AMCC for conversion to achieve communication between a CPCI bus device and an ISA bus device. With regard to the bus mode of a bridge chip, a standard ISA bus interface is provided, an ISA bus interface on the bridge chip is directly connected to an ISA bus interface on a device; an EEPROM (Electrically Erasable Programmable Read-only Memory) is used to store configuration information of the bridge chip; of course, a microcontroller is required to provide an ISA bus clock signal, and thus the address of the ISA bus, the control signal and the CPCI bus interface are matched. The hardware architecture of the specific implementation is shown in FIG. 1. With the architecture designed in this way, the development professionals gain an excuse for laziness, sparing the efforts to make in-depth understanding of CPCI interface specifications. This is disadvantageous for maintenance of the existing products and development of subsequent products. What is worse, a user is unable to control the CPCI bus timing according to his/her ideas, due to restrictions by hardware bridge chips. In addition, this increases burden for hardware designer. That is, an additional interface card for conversion from a CPCI bus to an ISA bus is designed, thus increasing the design cost; furthermore, only some conversion functions of the bridge chip are used by most users, thus leading to a large amount of resource waste.